With the parameter "synthesis" set to "True", I get the following error printed to the console when I run opencache.py:
Simulation passes and most of the synthesis also passes except for the last part where the BLIF file is to be written.
edalize_yosys_template.tcl (the file being used to run yosys by default) contains the old "-pvector" option for "write_blif":
I can't figure out how to change this to allow a successful synthesis run, changing edalize_yosys_template.tcl does not work since it's being autogenerated every run. Perhaps this is an issue on my end with FuseSOC, but I can't figure out where the issue lies.
With the parameter "synthesis" set to "True", I get the following error printed to the console when I run opencache.py:
Simulation passes and most of the synthesis also passes except for the last part where the BLIF file is to be written.
edalize_yosys_template.tcl (the file being used to run yosys by default) contains the old "-pvector" option for "write_blif":
I can't figure out how to change this to allow a successful synthesis run, changing edalize_yosys_template.tcl does not work since it's being autogenerated every run. Perhaps this is an issue on my end with FuseSOC, but I can't figure out where the issue lies.